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Fedora Electronic Lab

Digital Design

A HDL simulation environment that enables you to verify the functional and timing models of your design.

Thus, your Design teams can focus on improving existing methodologies with tools that scale across multiple levels of abstraction and design complexity.

Key Features

Supports both VHDL and Verilog designs.

Implementation of the VHDL language in accordance to the

o IEEE 1076-1987 standard

o IEEE 1076-1993 standard

o the protected types of VHDL00 (aka IEEE 1076a or IEEE 1076-2000)

o and non-standard third party libraries.

VPI functionality.

Export signals to a VCD file or a GHW file for visual inspection with a waveform viewer.

Pretty printing or cross references generation in HTML.

Makefile generation for any component in a design.

A graphical waveform viewer.

A Verilog simulator and synthesis tool for IEEE 1364-2001 standard

Achievements

Successfully compiled and run

a DLX processor and

a LEON1 SPARC processor.

Automatic layout generation from VHDL description via desired standard cell libraries.

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