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Digital Simulation
VLSI Layout and Verification
RTL and logic synthesis design
Circuit Simulation
PCB Layout and Circuit Design
Micro Controller (µC) Programming
and
Embedded Systems Development
Install the design tools
# yum install /tools/
Tools:
GHDL
GHDL is a VHDL simulator, using the GCC
technology.GHDL implements the VHDL
language according to the IEEE 1076-1987
or the IEEE 1076-1993 standard. It
compiles VHDL files and creates a
binary that simulates your design.
Qucs
Qucs is a circuit simulator with graphical
user interface. The software aims to
support all kinds of circuit simulation
types, e.g. DC, AC, S-parameter and
harmonic balance analysis.
Alliance
Alliance is a complete set of free CAD
tools and portable libraries for VLSI
design. It includes a VHDL compiler and
simulator, logic synthesis tools, and
automatic place and route tools.
FreeHDL
Yet another VHDL simulator.
iverlog
Icarus Verilog is a Verilog compiler that
generates a variety of engineering formats,
including simulation. It strives to be true
to the IEEE-1364 standard.
gtkwave
GTKWave is a waveform viewer that can view
VCD files produced by most Verilog simulation
tools, as well as LXT files produced by
certain Verilog simulation tools.
drawtiming
A command line tool for generating timing
diagrams from ASCII input files. The input
files use a structured language to represent
signal state transitions and interdependencies.
Fedora Electronic Lab
Digital Design
A HDL simulation environment that enables you to verify the functional and timing models of your design.
Thus, your Design teams can focus on improving existing methodologies with tools that scale across multiple levels of abstraction and design complexity.
Key Features
- Supports both VHDL and Verilog designs.
- Implementation of the VHDL language in accordance to the
o IEEE 1076-1987 standard
o IEEE 1076-1993 standard
o the protected types of VHDL00 (aka IEEE 1076a or IEEE 1076-2000)
o and non-standard third party libraries.
- VPI functionality.
- Export signals to a VCD file or a GHW file for visual inspection with a waveform viewer.
- Pretty printing or cross references generation in HTML.
- Makefile generation for any component in a design.
- A graphical waveform viewer.
- A Verilog simulator and synthesis tool for IEEE 1364-2001 standard
Achievements
Successfully compiled and run
- a DLX processor and
- a LEON1 SPARC processor.
Automatic layout generation from VHDL description via desired standard cell libraries.