Brochures
Table of Contents
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Digital Simulation
VLSI Layout and Verification
RTL and logic synthesis design
Circuit Simulation
PCB Layout and Circuit Design
Micro Controller (µC) Programming
and
Embedded Systems Development
Install the design tools
# yum install /tools/
Tools:
Magic
Magic is widely cited as being the easiest
tool to use for circuit layout, even for
people who ultimately rely on commercial
tools for their product design flow.
Alliance
Alliance is a complete set of free CAD
tools and portable libraries for VLSI
design. It includes a VHDL compiler and
simulator, logic synthesis tools, and
automatic place and route tools.
Toped
A cross-platform VLSI IC layout editor,
based on openGL and wxWidgets.
Netgen
Netgen is a tool for comparing netlists,
in analog or mixed-signal circuits that
cannot be simulated in reasonable time.
Fedora Electronic Lab
VLSI Design Layout and Checks
Includes
- A continuous DRC that operates in background and maintains an up-to-date picture of violations.
- A hierarchical circuit extractor that only re-extracts portions of the circuit that have changed.
Plowing that permits interactive stretching and compaction.
Routing tools that work under and around existing connections.
Logs and corner stitching to achieve efficient implementations.
Dedicated to training in sub-micron CMOS VLSI design with full editing facilities.
Supports technology files by the MOSIS foundry service.
Switch-level simulation of the layout, by considering transistors as ideal switches, or using RC time constants to predict the relative timing of events through extracted capacitance and lumped resistance values.
Ensures that layout connectivity matches the logical design represented by the schematic or netlist before tapeout by automatically
- extracting devices and nets formed across layout hierarchy and,
- comparing them to the schematic netlist. (LVS)
Generates GDS II stream format and Caltech Intermediate Form (CIF) from a given layout.
Achievement : Thick-film circuit layout using the Magic layout editor.