Brochures
Table of Contents
Home
Digital Simulation
VLSI Layout and Verification
RTL and logic synthesis design
Circuit Simulation
PCB Layout and Circuit Design
Micro Controller (µC) Programming
and
Embedded Systems Development
Install the design tools
# yum install /tools/
Tools:
Alliance
a complete set of free CAD tools and
portable libraries for VLSI design. It
includes a VHDL compiler and simulator,
logic synthesis tools, and automatic place
and route tools.pharosc
VLSI and ASIC Technology Standard
Cell Libraries
gds2pov
Creates attractive 3D pictures of a layout
Converts GDS2 layout file to POV-Ray
Fedora Electronic Lab
RTL and logic synthesis design flows
- Automatic schematic generation
- VHDL compilation and simulation
- Finite State Machines (FSM)
- Model checking and formal proof
- RTL and Logic synthesis
- Data-Path compilation
- Macro-cells generation
- Symbolic Pad cells
- Design rules checking
- Physical optimization and layout design flows.
- Complete RTL to CIF and GDSII flows.
- 7 extra standard cells up to a feature size of 0.13µm
- Read/write standard ins/outs including Verilog® and VHDL.
- Place and route
- Layout edition
- Automatic Layout generation
- Netlist extraction and verification
- Creates a POV-Ray (3D view) scene description file of the GDSII data.
