Fedora Electronic Lab

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  • Package List

Installation Procedures

On Fedora (11 and onwards)

yum groupinstall 'Electronic Lab'

EPEL-5 Repositories (Centos,RHEL,ScientificLinux)

yum install alliance dfu-programmer dinotrace eclipse-cdt eclipse-subclipse electric emacs-verilog-mode eqntott espresso-ab geda-docs geda-examples geda-gattrib geda-gnetlist geda-gschem geda-gsymcheck geda-symbols geda-utils gerbv gnucap gplcver gpsim gputils gtkwave gtkwave irsim iverilog iverilog linsmith magic netgen ngspice pcb perl-Hardware-Verilog-Parser perl-Hardware-Vhdl-Parser perl-ModelSim-List perl-Perlilog perl-Verilog perl-Verilog-Readmem qucs qucs tkcvs tkgate toped vhd2vl vrq xcircuit freehdl freehdl octave-forge

Package Description

LabPlot

Summary

LabPlot is for scientific 2D and 3D data and function plotting. The various display and analysis functions are explained in the handbook (KDE help center). LabPlot also provides a component for easily viewing the project files in Konqueror.

Supported Fedora branches

f10 f10 f11 f11 f12 f12
updates_testing updates updates_testing updates updates updates_testing
1.6.0.2-3.fc10 1.6.0.2-3.fc10
Sun Nov 16 12:43:13 2008
1.6.0.2-4.fc11 1.6.0.2-4.fc11 1.6.0.2-8.fc12 1.6.0.2-8.fc12

alliance

Summary

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler. Alliance is the result of more than ten years effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router. You are kindly requested to mention " Designed with alliance (c) LIP6, Université Pierre et Marie Curie" so as to spread the word about "alliance CAD system" and its development team. Alliance provides CAD tools covering most of all the digital design flow:
  • VHDL Compilation and Simulation
  • Model checking and formal proof
  • RTL and Logic synthesis
  • Data-Path compilation
  • Macro-cells generation
  • Place and route
  • Layout edition
  • Netlist extraction and verification
  • Design rules checking alliance is listed among Fedora Electronic Lab (FEL) packages.

    Supported Fedora branches

  • 5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    5.0-31.20090901snap.el5 5.0-31.20090901snap.el5 5.0-31.20090901snap.fc10 5.0-31.20090901snap.fc10 5.0-31.20090901snap.fc11 5.0-31.20090901snap.fc11 5.0-31.20090901snap.fc12 5.0-31.20090901snap.fc12

    archimedes

    Summary

    Archimedes is a package for the design and simulation of submicron semiconductor devices. It is a 2D Fast Monte Carlo simulator which can take into account all the relevant quantum effects, thank to the implementation of the Bohm effective potential method. The physics and geometry of a general device is introduced by typing a simple script, which makes, in this sense, Archimedes a powerful tool for the simulation of quite general semiconductor devices.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.8.0-1.fc10 0.8.0-1.fc10 0.8.0-2.fc11 0.8.0-2.fc11 0.8.0-4.fc12 0.8.0-4.fc12

    arm-gp2x-linux-SDL

    Summary

    This is a Cross Compiled version of the SDL Library, which can be used to compile and link binaries for the arm-gp2x-linux platform, instead of for the native noarch platform.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.2.9-4.fc8 1.2.9-4.fc8 1.2.9-5.fc11 1.2.9-5.fc11 1.2.9-6.fc12 1.2.9-6.fc12

    arm-gp2x-linux-binutils

    Summary

    This is a Cross Compiling version of GNU binutils, which can be used to assemble and link binaries for the arm-gp2x-linux platform, instead of for the native i386 platform.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2.16.1-5.fc9 2.16.1-5.fc9 2.16.1-6.fc11 2.16.1-6.fc11 2.16.1-7.fc12 2.16.1-7.fc12

    arm-gp2x-linux-gcc

    Summary

    This is a Cross Compiling version of GNU GCC, which can be used to compile programs for the arm-gp2x-linux platform, instead of for the native i386 platform.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    4.1.2-9.fc10 4.1.2-9.fc10 4.1.2-10.fc11 4.1.2-10.fc11 4.1.2-11.fc12 4.1.2-11.fc12

    arm-gp2x-linux-glibc

    Summary

    This is a Cross Compiled version of the GNU C Library, which can be used to compile and link binaries for the arm-gp2x-linux platform, instead of for the native noarch platform.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2.3.6-5.fc9 2.3.6-5.fc9 2.3.6-6.fc11 2.3.6-6.fc11 2.3.6-7.fc12 2.3.6-7.fc12

    arm-gp2x-linux-kernel-headers

    Summary

    Kernel headers for Cross Compiling to arm-gp2x-linux.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2.6.12.0-2.fc8 2.6.12.0-2.fc8 2.6.12.0-3.fc11 2.6.12.0-3.fc11 2.6.12.0-4.fc12 2.6.12.0-4.fc12

    arm-gp2x-linux-zlib

    Summary

    This is a Cross Compiled version of the zlib Library, which can be used to compile and link zlib using applications for the arm-gp2x-linux platform, instead of for the native noarch platform.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.2.3-6.fc8 1.2.3-6.fc8 1.2.3-7.fc11 1.2.3-7.fc11 1.2.3-8.fc12 1.2.3-8.fc12

    avarice

    Summary

    Program for interfacing the Atmel JTAG ICE to GDB to allow users to debug their embedded AVR target

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2.6-3.fc10 2.6-3.fc10 2.6-4.fc11 2.6-4.fc11 2.6-5.fc12 2.6-5.fc12

    avr-binutils

    Summary

    This is a Cross Compiling version of GNU binutils, which can be used to assemble and link binaries for the avr platform, instead of for the native i386 platform.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2.18-2.fc9 2.18-2.fc9 2.18-4.fc11 2.18-4.fc11 2.18-5.fc12 2.18-5.fc12

    avr-gcc

    Summary

    This is a Cross Compiling version of GNU GCC, which can be used to compile for the avr platform, instead of for the native i386 platform.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    4.3.3-1.fc10 4.3.3-1.fc10 4.3.3-2.fc11 4.3.3-2.fc11 4.3.3-3.fc12 4.3.3-3.fc12

    avr-gdb

    Summary

    This is a special version of GDB, the GNU Project debugger, for (remote) debugging avr binaries. GDB allows you to see what is going on inside another program while it executes or what another program was doing at the moment it crashed.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    6.6-8.fc9 6.6-8.fc9 6.6-9.fc11 6.6-9.fc11 6.6-11.fc12 6.6-11.fc12

    avra

    Summary

    Avra is an assembler for Atmel's AVR 8-bit RISC microcontollers. It is mostly compatible with Atmel's own assembler, but provides new features such as better macro support and additional preprocessor directives. This package also contains various device definition files.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.2.3-4.fc10 1.2.3-4.fc10 1.2.3-4.fc11 1.2.3-4.fc11 1.2.3-4.fc12 1.2.3-4.fc12

    avrdude

    Summary

    AVRDUDE is a program for programming Atmel's AVR CPU's. It can program the Flash and EEPROM, and where supported by the serial programming protocol, it can program fuse and lock bits. AVRDUDE also supplies a direct instruction mode allowing one to issue any programming instruction to the AVR chip regardless of whether AVRDUDE implements that specific feature of a particular chip.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    5.5-3.fc9 5.5-3.fc9 5.8-1.fc11 5.8-1.fc11 5.8-1.fc12 5.8-1.fc12

    dfu-programmer

    Summary

    A linux based command-line programmer for Atmel chips with a USB bootloader supporting ISP. This is a mostly Device Firmware Update (DFU) 1.0 compliant user-space application. Supports all DFU enabled Atmel chips with USB support.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.4.3-2.el5 0.4.3-2.el5 0.5.1-1.fc10 0.5.1-1.fc10 0.5.1-2.fc11 0.5.1-2.fc11 0.5.1-3.fc12 0.5.1-3.fc12

    dinotrace

    Summary

    Dinotrace is a waveform viewer which understands Verilog Value Change Dumps, ASCII, and other trace formats. It allows placing cursors, highlighting signals, searching, printing, and other capabilities superior to many commercial waveform viewers. Dinotrace is optimized for rapid debugging. With VTRACE, a simulation failure will automatically place cursors where errors occur, add comments visible in the wave form viewer. Four mouse clicks and the errors will be highlighted in the log files, and the values of signals at the error will be seen in the source.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    9.4a-5.el5 9.4a-5.el5 9.4a-3.fc10 9.4a-3.fc10 9.4a-3.fc11 9.4a-3.fc11 9.4a-5.fc12 9.4a-5.fc12

    drawtiming

    Summary

    A command line tool for generating timing diagrams from ASCII input files. The input files use a structured language to represent signal state transitions and interdependencies. Raster image output support is provided by ImageMagick. It can be used for VHDL or verilog presentations.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.6.2-3.fc10 0.6.2-3.fc10 0.6.2-5.fc11 0.6.2-5.fc11 0.6.2-6.fc12 0.6.2-6.fc12

    eclipse-cdt

    Summary

    Eclipse features and plugins that are useful for C and C++ development.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    3.1.2-8.el5 3.1.2-8.el5 5.0.2-4.fc10 5.0.2-4.fc10 5.0.2-4.fc11 5.0.2-4.fc11 6.0.0-10.fc12 6.0.0-10.fc12

    eclipse-eclox

    Summary

    Eclox is a doxygen frontend plug-in for eclipse. It aims to provide a slim and sleek integration of the code documentation process into eclipse.

    Supported Fedora branches

    f11 f11 f12 f12
    updates updates_testing updates updates_testing
    0.8.0-2.20090616svn.fc11
    Sun Jul 12 20:22:13 2009
    0.8.0-2.20090616svn.fc11 0.8.0-3.20090616svn.fc12 0.8.0-3.20090616svn.fc12

    eclipse-epic

    Summary

    EPIC is an open source Perl IDE based on the Eclipse platform. Features supported are syntax highlighting, on-the-fly syntax check, content assist, perldoc support, source formatter, templating support, a regular expression view and a Perl debugger.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.6.33-1.fc10 0.6.33-1.fc10 0.6.35-1.fc11 0.6.35-1.fc11
    Tue Jun 2 22:55:49 2009
    0.6.35-2.fc12 0.6.35-2.fc12

    eclipse-subclipse

    Summary

    Subclipse is an Eclipse plugin that adds Subversion integration to the Eclipse IDE.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    1.2.2-2.el5 1.2.2-2.el5 1.4.7-3.fc10 1.4.7-3.fc10
    Tue Apr 7 17:45:04 2009
    1.6.0-1.fc11 1.6.0-1.fc11 1.6.5-1.fc12 1.6.5-1.fc12

    eclipse-texlipse

    Summary

    Texlipse is a plugin that adds Latex editing support for the popular Eclipse IDE. Key features include: Syntax highlight, command completion, bibliography completion, outline navigation and automatic building.

    Supported Fedora branches

    f11 f11 f12 f12
    updates updates_testing updates updates_testing
    1.3.0-2.20090829cvs.fc11
    Sun Aug 30 00:37:37 2009
    1.3.0-2.20090829cvs.fc11 1.3.0-2.20090829cvs.fc12 1.3.0-2.20090829cvs.fc12

    eclipse-veditor

    Summary

    Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.6.3-3.fc10 0.6.3-3.fc10
    Wed Jun 17 19:38:04 2009
    0.6.3-3.fc11 0.6.3-3.fc11
    Wed Jun 17 19:36:29 2009
    0.6.3-4.fc12 0.6.3-4.fc12

    electric

    Summary

    Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including custom IC layout (ASICs), schematic drawing, hardware description language specifications, and electro-mechanical hybrid layout.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    8.07-2.el5 8.07-2.el5 8.09-1.fc10
    Thu Jul 30 12:53:11 2009
    8.08-1.fc10
    Wed Jan 7 02:10:06 2009
    8.09-1.fc11
    Thu Jul 30 12:05:14 2009
    8.08-3.fc11 8.09-1.fc12 8.09-1.fc12

    emacs-verilog-mode

    Summary

    Verilog-mode.el is a free Verilog mode for Emacs which provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time.

    Supported Fedora branches

    5E 5E f12 f12
    epel_testing epel updates updates_testing
    531-1.el5 531-1.el5 531-1.fc12 531-1.fc12

    eqntott

    Summary

    Converts Boolean logic expressions into a truth table that is useful for preparing input to espresso package for logic minimization, converting logic expressions into simpler forms, and for creating truth tables.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    9.0-2.el5 9.0-2.el5 9.0-2.fc10 9.0-2.fc10 9.0-2.fc11 9.0-2.fc11 9.0-2.fc12 9.0-2.fc12

    espresso-ab

    Summary

    Espresso takes as input a two-level representation of a two-valued (or multiple-valued) Boolean function, and produces a minimal equivalent representation. It is a boolean logic minimization tool.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    1.0-1.el5 1.0-1.el5 1.0-1.fc10 1.0-1.fc10 1.0-1.fc11 1.0-1.fc11 1.0-1.fc12 1.0-1.fc12

    fped

    Summary

    fped is an editor that allows the interactive creation of footprints of electronic components. Footprint definitions are stored in a text format that resembles a programming language. The language is constrained such that anything that can be expressed in the textual definition also has a straightforward equivalent operation that can be performed through the GUI.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0-0.1.r5664.fc10 0-0.1.r5664.fc10 0-0.1.r5664.fc11 0-0.1.r5664.fc11 0-0.1.r5664.fc12 0-0.1.r5664.fc12

    freehdl

    Summary

    A project to develop a free, open source, GPL'ed VHDL simulator for Linux.

    Supported Fedora branches

    4E 4E 5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel epel epel_testing updates updates_testing updates_testing updates updates updates_testing
    0.0.6-1.el4 0.0.6-1.el4 0.0.6-1.el5 0.0.6-1.el5 0.0.7-1.fc10
    Thu May 7 08:29:07 2009
    0.0.7-1.fc10 0.0.7-1.fc11 0.0.7-1.fc11
    Thu May 7 08:44:53 2009
    0.0.7-2.fc12 0.0.7-2.fc12

    gds2pov

    Summary

    GDS2POV is a program to take a GDS2 layout file and output a POV-Ray scene description file of the GDS2 data. This allows the creation of attractive 3D pictures of a layout. GDS2POV is mostly used by VLSI designers.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.20080229-1.fc9 0.20080229-1.fc9 0.20080229-2.fc11 0.20080229-2.fc11 0.20080229-3.fc12 0.20080229-3.fc12

    geda-docs

    Summary

    This package contains documentation and examples for the gEDA project.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10 20081231-2.fc11 20081231-2.fc11 20081231-3.fc12 20081231-3.fc12

    geda-examples

    Summary

    This package contains circuit examples for the gEDA project.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10
    Sun Jan 11 23:24:11 2009
    20081231-2.fc11 20081231-2.fc11 20081231-3.fc12 20081231-3.fc12

    geda-gattrib

    Summary

    Gattrib is gEDA's attribute editor. It reads a set of gschem .sch files (schematic files), and creates a spreadsheet showing all components in rows, with the associated component attributes listed in the columns. It allows the user to add, modify, or delete component attributes outside of gschem, and then save the .sch files back out. When it is completed, it will allow the user to edit attributes attached to components, nets, and pins. (Currently, only component attribute editing is implemented; pin attributes are displayed only, and net attributes are TBD.) Gattrib is gEDA's attribute editor. It reads a set of gschem .sch files (schematic files), and creates a spreadsheet showing all components in rows, with the associated component attributes listed in the columns. It allows the user to add, modify, or delete component attributes outside of gschem, and then save the .sch files back out. When it is completed, it will allow the user to edit attributes attached to components, nets, and pins. (Currently, only component attribute editing is implemented; pin attributes are displayed only, and net attributes are TBD.)

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10 20081231-3.fc11 20081231-3.fc11 20081231-3.fc11 20081231-3.fc11

    geda-gnetlist

    Summary

    Gnetlist generates netlists from schematics drawn with gschem (the gEDA schematic editor). Possible output formats are: - native - tango - spice - allegro - PCB - verilog and others.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10 20081231-2.fc11 20081231-2.fc11 20081231-3.fc12 20081231-3.fc12

    geda-gschem

    Summary

    Gschem is an electronics schematic editor. It is part of the gEDA project.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10 20081231-3.fc11 20081231-3.fc11 20081231-4.fc12 20081231-4.fc12

    geda-gsymcheck

    Summary

    Gsymcheck is a utility to check symbols for gschem. It is part of the gEDA project.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10 20081231-2.fc11 20081231-2.fc11 20081231-3.fc12 20081231-3.fc12

    geda-symbols

    Summary

    This package contains a bunch of symbols of electronic devices used by gschem, the gEDA project schematic editor.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10 20081231-2.fc11 20081231-2.fc11 20081231-3.fc12 20081231-3.fc12

    geda-utils

    Summary

    Several utilities for the gEDA project.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20081220-1.el5 20081220-1.el5 20081231-1.fc10 20081231-1.fc10 20081231-2.fc11 20081231-2.fc11 20081231-3.fc12 20081231-3.fc12

    gerbv

    Summary

    Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files are generated from PCB CAD system and sent to PCB manufacturers as basis for the manufacturing process. The standard supported by gerbv is RS-274X. gerbv also supports drill files. The format supported are known under names as NC-drill or Excellon. The format is a bit undefined and different EDA-vendors implement it different. gerbv is listed among Fedora Electronic Lab (FEL) packages.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    2.3.0-2.el5 2.3.0-2.el5 2.3.0-2.fc10 2.3.0-2.fc10
    Sun Sep 13 17:39:26 2009
    2.3.0-2.fc11 2.3.0-2.fc11
    Sun Sep 13 17:38:23 2009
    2.3.0-3.fc12 2.3.0-3.fc12

    ghdl

    Summary

    GHDL is a VHDL simulator, using the GCC technology. VHDL is a language standardized by the IEEE, intended for developing electronic systems. GHDL implements the VHDL language according to the IEEE 1076-1987 or the IEEE 1076-1993 standard. It compiles VHDL files and creates a binary that simulates (or executes) your design. GHDL does not do synthesis: it cannot translate your design into a netlist. Since GHDL is a compiler (i.e., it generates object files), you can call functions or procedures written in a foreign language, such as C, C++, or Ada95.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.27-0.110svn.3.fc10 0.27-0.110svn.3.fc10 0.27-0.110svn.7.fc11 0.27-0.110svn.7.fc11 0.28-0.130svn.0.fc12 0.28-0.130svn.0.fc12

    gnucap

    Summary

    The primary component is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, fourier analysis, and ac analysis. Spice compatible models for the MOSFET (level 1-7), BJT, and diode are included in this release. Gnucap is not based on Spice, but some of the models have been derived from the Berkeley models. Unlike Spice, the engine is designed to do true mixed-mode simulation. Most of the code is in place for future support of event driven analog simulation, and true multi-rate simulation.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.35-6.el5 0.35-6.el5 0.35-4.fc9 0.35-4.fc9 0.35-5.fc11 0.35-5.fc11 0.35-6.fc12 0.35-6.fc12

    gnuradio

    Summary

    GNU Radio is a collection of software that when combined with minimal hardware, allows the construction of radios where the actual waveforms transmitted and received are defined by software. What this means is that it turns the digital modulation schemes used in today's high performance wireless devices into software problems.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    3.1.3-2.fc10 3.1.3-2.fc10
    Sat Dec 20 12:21:57 2008
    3.2.2-1.fc11 3.2.2-1.fc11
    Wed Jul 29 13:26:36 2009
    3.2.2-1.fc12 3.2.2-1.fc12

    gnusim8085

    Summary

    GNUSim8085 is a graphical simulator for Intel 8085 microprocessor assembly language. It has some very nice features including a keypad which can be used to write assembly language programs with much ease. It also has stack, memory and port viewers which can be used for debugging the programs.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.3.5-4.fc10 1.3.5-4.fc10 1.3.5-4.fc11 1.3.5-4.fc11 1.3.5-5.fc12 1.3.5-5.fc12

    gplcver

    Summary

    Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM. GPL Cver is an older version of Cver that is released under the GNU General Public License. A newer and faster commercial version of Cver is available from Pragmatic C Software Corp.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    2.11a-2.el5 2.11a-2.el5 2.11a-2.fc10 2.11a-2.fc10 2.11a-2.fc11 2.11a-2.fc11 2.11a-2.fc12 2.11a-2.fc12

    gpsim

    Summary

    gpsim is a simulator for Microchip (TM) PIC (TM) microcontrollers. It supports most devices in Microchip's 12-bit, 14bit, and 16-bit core families. In addition, gpsim supports dynamically loadable modules such as LED's, LCD's, resistors, etc. to extend the simulation environment beyond the PIC.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.24.0-2.el5 0.24.0-2.el5 0.23.0-1.fc10 0.23.0-1.fc10
    Sun Mar 29 23:51:53 2009
    0.23.0-4.fc11 0.23.0-4.fc11 0.24.0-1.fc12 0.24.0-1.fc12

    gputils

    Summary

    This is a collection of development tools for Microchip (TM) PIC (TM) microcontrollers. This is ALPHA software: there may be serious bugs in it, and it's nowhere near complete. gputils currently only implements a subset of the features available with Microchip's tools. See the documentation for an up-to-date list of what gputils can do.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.13.7-1.el5 0.13.7-1.el5 0.13.7-1.fc10 0.13.7-1.fc10 0.13.7-1.fc11 0.13.7-1.fc11 0.13.7-2.fc12 0.13.7-2.fc12

    gresistor

    Summary

    To allow for identification, resistors are usually marked with colored bands. Often refereed to as color codes, these markings are indicative of their resistance, tolerance and temperature coefficient. gResistor is a great program that will help you translate a resistor color codes into a readable value.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.0.1-12.fc10 0.0.1-12.fc10 0.0.1-15.fc11 0.0.1-15.fc11 0.0.1-16.fc12 0.0.1-16.fc12

    gsim85

    Summary

    It is an 8085 simulator. it is having very user friendly graphical user interface. It can be used to test 8085 programs before actualy implementing them on target board.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.2-4.fc10 0.2-4.fc10 0.2-5.fc11 0.2-5.fc11 0.2-6.fc12 0.2-6.fc12

    gspiceui

    Summary

    GspiceUI is listed among the Fedora Electronic Lab (FEL) packages. GNU Spice GUI is intended to provide a GUI to freely available Spice electronic cicuit simulators eg.GnuCAP, Ng-Spice. It uses gNetList to convert schematic files to net list files and gWave to display simulation results. gSchem is used as the schematic generation/viewing tool.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.9.97-1.fc10 0.9.97-1.fc10 0.9.65-5.fc11 0.9.65-5.fc11 0.9.97-1.fc12 0.9.97-1.fc12

    gtkterm

    Summary

    Simple GUI terminal used to communicate with the serial port. Similar to minicom or hyperterminal.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.99.5-9.fc9 0.99.5-9.fc9 0.99.5-10.fc11 0.99.5-10.fc11 0.99.5-11.fc12 0.99.5-11.fc12

    gtkwave

    Summary

    GTKWave is a waveform viewer that can view VCD files produced by most Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools.

    Supported Fedora branches

    4E 4E 5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel epel epel_testing updates updates_testing updates_testing updates updates updates_testing
    3.1.12-1.el4 3.1.12-1.el4 3.1.12-1.el5 3.1.12-1.el5 3.1.13-1.fc10 3.1.13-1.fc10 3.2.1-2.fc11 3.2.1-2.fc11 3.2.3-1.fc12 3.2.3-1.fc12

    gwave

    Summary

    Gwave is a waveform viewer, intended originaly for displaying the output of analog simulators such as spice, but also useful for other purposes. Gwave can read tabluar ascii files in addition to the specialized output files from Spice3, NGSpice, and Hspice. It displays the data as 2-D plots, and allows for scrolling, zooming, and measuring the waveforms. Install gwave if you need 2-D interactive display of analog waveforms or other tabluar data. gwave is listed among Fedora Electronic Lab (FEL) packages.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2-15.20090124snap.fc10 2-15.20090124snap.fc10 2-15.20090124snap.fc11 2-15.20090124snap.fc11 2-16.20090124snap.fc12 2-16.20090124snap.fc12

    irsim

    Summary

    IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    9.7.68-1.el5 9.7.68-1.el5 9.7.68-1.fc10 9.7.68-1.fc10 9.7.68-2.fc11 9.7.68-2.fc11 9.7.68-3.fc12 9.7.68-3.fc12

    iverilog

    Summary

    Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.

    Supported Fedora branches

    4E 4E 5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel epel epel_testing updates updates_testing updates_testing updates updates updates_testing
    0.9.20070608-1.el4 0.9.20070608-1.el4 0.9.20070608-1.el5 0.9.20070608-1.el5 0.9.20090423-5.fc10 0.9.20090423-5.fc10 0.9.20090423-5.fc11 0.9.20090423-5.fc11 0.9.20090423-6.fc12 0.9.20090423-6.fc12

    kdesvn

    Summary

    KDESvn is a frontend to the subversion vcs. In difference to most other tools it uses the subversion C-Api direct via a c++ wrapper made by Rapid SVN and doesn't parse the output of the subversion client. So it is a real client itself instead of a frontend to the command line tool. It is designed for the K-Desktop environment and uses all of the goodies it has. It is planned for future that based on the native client some plugins for konqueror and/or kate will made.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.4.1-1.fc10 1.4.1-1.fc10
    Fri Oct 2 09:27:20 2009
    1.4.1-1.fc11 1.4.1-1.fc11
    Fri Oct 2 09:12:47 2009
    1.4.1-1.fc12 1.4.1-1.fc12

    kicad

    Summary

    Kicad is an EDA software to design electronic schematic diagrams and printed circuit board artwork up to 16 layers. Kicad is a set of four softwares and a project manager: - Eeschema: schematic entry - Pcbnew: board editor - Gerbview: GERBER viewer (photoplotter documents) - Cvpcb: footprint selector for components used in the circuit design - Kicad: project manager

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2007.07.09-4.fc10 2007.07.09-4.fc10 2009.07.07-4.rev1863.fc11 2009.07.07-4.rev1863.fc11
    Tue Aug 25 14:09:42 2009
    2009.07.07-4.rev1863.fc12 2009.07.07-4.rev1863.fc12

    ktechlab

    Summary

    KTechlab is a development and simulation environment for microcontrollers and electronic circuits. KTechlab consists of several well-integrated components: A circuit simulator, capable of simulating logic, linear devices and some nonlinear devices.
  • Integration with gpsim, allowing PICs to be simulated in circuit.
  • A schematic editor, which provides a rich real-time feedback of the simulation.
  • A flowchart editor, allowing PIC programs to be constructed visually.
  • MicroBASIC; a BASIC-like compiler for PICs, written as a companion program to KTechlab.
  • An embedded Kate part, which provides a powerful editor for PIC programs.
  • Integrated assembler and disassembler via gpasm and gpdasm.

    Supported Fedora branches

  • f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.3.70-1.20090304svn.fc10 0.3.70-1.20090304svn.fc10 0.3.70-1.20090304svn.fc11 0.3.70-1.20090304svn.fc11 0.3.70-3.20090304svn.fc12 0.3.70-3.20090304svn.fc12

    linsmith

    Summary

    linSmith is a Smith Charting program. It's main features are:
  • Definition of multiple load impedances
  • Addition of discrete and line components
  • A 'virtual' component switches from impedance to admittance to help explaining parallel components
  • The chart works in real impedances
  • Load and circuit configuration is stored separately, permitting several solutions without re-defining the other

    Supported Fedora branches

  • 5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.99.12-1.el5 0.99.12-1.el5 0.99.12-1.fc10 0.99.12-1.fc10 0.99.12-1.fc11 0.99.12-1.fc11 0.99.12-2.fc12 0.99.12-2.fc12

    magic

    Summary

    Magic is a venerable VLSI layout tool. Magic VLSI remains popular with universities and small companies. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    7.5.168-1.el5 7.5.168-1.el5 8.0.54-1.fc10 7.5.169-1.fc10 8.0.54-1.fc11 7.5.169-2.fc11 8.0.54-1.fc12 8.0.54-1.fc12

    mcu8051ide

    Summary

    Integrated Development Enviroment for some MCS-51 based microcontrollers (e.g. AT89S8253). Supported languages are assembly and C.

    Supported Fedora branches

    5E f10 f10 f11 f11 f12 f12
    epel_testing updates_testing updates updates_testing updates updates updates_testing
    1.1-4.el5
    Mon Jul 6 07:22:24 2009
    1.3.1-1.fc10 1.3.1-1.fc10
    Sun Oct 25 19:00:49 2009
    1.3.1-1.fc11 1.3.1-1.fc11
    Sun Oct 25 19:01:02 2009
    1.1-5.fc12 1.1-5.fc12

    minicom

    Summary

    Minicom is a simple text-based modem control and terminal emulation program somewhat similar to MSDOS Telix. Minicom includes a dialing directory, full ANSI and VT100 emulation, an (external) scripting language, and other features.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2.3-3.fc10 2.3-3.fc10 2.3-4.fc11 2.3-4.fc11 2.3-6.fc12 2.3-6.fc12

    netgen

    Summary

    Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    1.3.7-17.el5 1.3.7-17.el5 1.3.7-17.fc10 1.3.7-17.fc10 1.3.7-18.fc11 1.3.7-18.fc11 1.3.7-19.fc12 1.3.7-19.fc12

    ngspice

    Summary

    Ngspice is a general-purpose circuit simulator program. It implements three classes of analysis: - Nonlinear DC analyses - Nonlinear Transient analyses - Linear AC analyses Ngspice implements the usual circuits elements, like resistors, capacitors, inductors (single or mutual), transmission lines and a growing number of semiconductor devices like diodes, bipolar transistors, mosfets (both bulk and SOI), mesfets, jfet and HFET. Ngspice implements the EKV model but it cannot be distributed with the package since its license does not allow to redistribute EKV source code. Ngspice integrates Xspice, a mixed-mode simulator built upon spice3c1 (and then some tweak is necessary merge it with spice3f5). Xspice provides a codemodel interface and an event-driven simulation algorithm. Users can develop their own models for devices using the codemodel interface. It could be used for VLSI simulations as well.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    18-1.el5 18-1.el5 19-1.fc10 19-1.fc10 19-1.fc11 19-1.fc11 19-1.fc12 19-1.fc12

    octave-forge

    Summary

    Octave-forge is a community project for collaborative development of Octave extensions. The extensions in this package include additional data types, and functions for a variety of different applications including signal and image processing, communications, control, optimization, statistics, and symbolic math.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    20071212-6.el5 20071212-6.el5 20080831-2.fc10 20080831-2.fc10 20090607-15.fc11 20090607-15.fc11 20090607-15.fc12 20090607-15.fc12

    openocd

    Summary

    The Open On-Chip Debugger (OpenOCD) provides debugging, in-system programming and boundary-scan testing for embedded devices. Various different boards, targets, and interfaces are supported to ease development time. Install OpenOCD if you are looking for an open source solution for hardware debugging.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.2.0-4.fc10 0.2.0-4.fc10 0.2.0-4.fc11 0.2.0-4.fc11 0.2.0-4.fc12 0.2.0-4.fc12

    pcb

    Summary

    PCB is an interactive printed circuit board editor for the X window system. PCB includes a rats nest feature, design rule checking, and can provide industry standard RS-274-X (Gerber), NC drill, and centroid data (X-Y data) output for use in the board fabrication and assembly process. PCB offers high end features such as an autorouter and trace optimizer which can tremendously reduce layout time.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.20081128-4.el5 0.20081128-4.el5 0.20081128-1.fc10 0.20081128-1.fc10 0.20081128-2.fc11 0.20081128-2.fc11 0.20081128-4.fc12 0.20081128-4.fc12

    perl-Hardware-Verilog-Parser

    Summary

    This module defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.13-1.el5 0.13-1.el5 0.13-1.fc10 0.13-1.fc10
    Sun Dec 28 23:42:22 2008
    0.13-2.fc11 0.13-2.fc11 0.13-3.fc12 0.13-3.fc12

    perl-Hardware-Vhdl-Lexer

    Summary

    Hardware::Vhdl::Lexer splits VHDL code into lexical tokens. To use it, you need to first create a lexer object, passing in something which will supply chunks of VHDL code to the lexer. Repeated calls to the get_next_token method of the lexer will then return VHDL tokens (in scalar context) or a token type code and the token (in list context). get_next_token returns undef when there are no more tokens to be read.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.00-2.fc10 1.00-2.fc10
    Wed Dec 24 15:23:08 2008
    1.00-3.fc11 1.00-3.fc11 1.00-4.fc12 1.00-4.fc12

    perl-Hardware-Vhdl-Parser

    Summary

    This module defines the complete grammar needed to parse any VHDL code. By overloading this grammar, it is possible to easily create perl scripts which run through VHDL code and perform specific functions.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.12-2.el5 0.12-2.el5 0.12-2.fc10 0.12-2.fc10
    Mon Dec 15 23:17:10 2008
    0.12-3.fc11 0.12-3.fc11 0.12-4.fc12 0.12-4.fc12

    perl-Hardware-Vhdl-Tidy

    Summary

    This module auto-indents VHDL source code. It may be extended in future to do other types of code prettification.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.8-2.fc10 0.8-2.fc10
    Wed Jan 7 22:54:10 2009
    0.8-4.fc11 0.8-4.fc11 0.8-5.fc12 0.8-5.fc12

    perl-ModelSim-List

    Summary

    This module provides a class named ModelSim::List with which the EDA tester can easily check in the signals contained in the files generated by ModelSim's "write list" command in a programming manner.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.06-1.el5 0.06-1.el5 0.06-1.fc10 0.06-1.fc10
    Sun Dec 28 22:44:10 2008
    0.06-2.fc11 0.06-2.fc11 0.06-3.fc12 0.06-3.fc12

    perl-Perlilog

    Summary

    Perlilog is a command-line tool which generates Verilog modules from a set of files, which come in several other formats. It was originally designed to integrate Verilog IP cores.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.3-1.el5 0.3-1.el5 0.3-1.fc10 0.3-1.fc10
    Sun Dec 28 22:44:27 2008
    0.3-2.fc11 0.3-2.fc11 0.3-3.fc12 0.3-3.fc12

    perl-SystemC-Vregs

    Summary

    A Vregs object contains a documentation "package" containing enumerations, definitions, classes, and registers.

    Supported Fedora branches

    5E f10 f10 f11 f11 f12 f12
    epel_testing updates_testing updates updates_testing updates updates updates_testing
    1.463-1.el5
    Thu May 21 20:59:28 2009
    1.463-1.fc10 1.463-1.fc10
    Fri May 22 11:06:45 2009
    1.463-1.fc11 1.463-1.fc11
    Thu Jun 11 10:23:38 2009
    1.463-2.fc12 1.463-2.fc12

    perl-SystemPerl

    Summary

    SystemPerl is a version of the SystemC language. It is designed to expand text so that needless repetition in the language is minimized. By using sp_preproc, SystemPerl files can be expanded into C++ files at compile time, or expanded in place to make them valid stand-alone SystemC files.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.321-1.fc10 1.321-1.fc10 1.330-1.fc11 1.330-1.fc11 1.330-2.fc12 1.330-2.fc12

    perl-Verilog

    Summary

    This package provides functions to support writing utilities that use the Verilog language.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    3.212-1.el5 3.212-1.el5 3.212-1.fc10 3.212-1.fc10 3.212-1.fc11 3.212-1.fc11 3.212-1.fc12 3.212-1.fc12

    perl-Verilog-CodeGen

    Summary

    Provides an object-oriented environment to generate Verilog code for modules and testbenches. The Verilog::CodeGen module provides two functions, one to create a code template and another to create a Perl module which contains the device library. This module , DeviceLibs::YourDesign, provides the class methods and contains the objects for every Verilog module; the objects are created based on a fixed template. The purpose of this module is to allow the generation of customized Verilog modules. A Verilog module can have a large number of parameters like input and output bus width, buffer depth, signal delay etc. The code generator allows to create an object that will generate the Verilog module code for arbitraty values of the parameters.

    Supported Fedora branches

    5E f10 f10 f11 f11 f12 f12
    epel_testing updates_testing updates updates_testing updates updates updates_testing
    0.9.4-1.el5
    Wed Mar 25 00:06:47 2009
    0.9.4-1.fc10 0.9.4-1.fc10
    Wed Mar 25 00:06:06 2009
    0.9.4-1.fc11 0.9.4-1.fc11 0.9.4-2.fc12 0.9.4-2.fc12

    perl-Verilog-Readmem

    Summary

    The Verilog Hardware Description Language (HDL) provides a convenient way to load a memory during logic simulation. The $readmemh() and $readmemb() system tasks are used in the HDL source code to import the contents of a text file into a memory variable.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.04-1.el5 0.04-1.el5 0.04-1.fc10 0.04-1.fc10
    Wed Mar 4 21:28:25 2009
    0.04-1.fc11 0.04-1.fc11 0.04-2.fc12 0.04-2.fc12

    pharosc

    Summary

    VLSI and ASIC Technology Standard Cell Libraries. There are five new open source standard cell libraries, the
  • vsclib,
  • wsclib,
  • vxlib,
  • vgalib and
  • rgalib. They have been drawn with the Graal software from Alliance, part of an extensive open source software suite for designing integrated circuits with a standard cell design methodology.

    Supported Fedora branches

  • f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    8.3-1.fc8 8.3-1.fc8 8.3-2.fc11 8.3-2.fc11 8.3-3.fc12 8.3-3.fc12

    picocom

    Summary

    As its name suggests, [picocom] is a minimal dumb-terminal emulation program. It is, in principle, very much like minicom, only it's "pico" instead of "mini"! It was designed to serve as a simple, manual, modem configuration, testing, and debugging tool. It has also served (quite well) as a low-tech "terminal-window" to allow operator intervention in PPP connection scripts (something like the ms-windows "open terminal window before / after dialing" feature). It could also prove useful in many other similar tasks. It is ideal for embedded systems since its memory footprint is minimal (less than 20K, when stripped).

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.4-6.fc10 1.4-6.fc10 1.4-7.fc11 1.4-7.fc11 1.4-8.fc12 1.4-8.fc12

    picprog

    Summary

    Picprog is a simple program for burning programs to various Microchip PIC microcontrollers via several types of serial port programmers.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.9.0-4.fc10 1.9.0-4.fc10 1.9.0-4.fc11 1.9.0-4.fc11 1.9.0-4.fc12 1.9.0-4.fc12

    pikdev

    Summary

    PiKdev is a simple IDE dedicated to the development of PIC based applications under KDE. Features: - Integrated editor - Project management - Integrated programming engine for 12, 14 and 16 bits PIC (flash or EPROM technology) - Support for parallel and serial port programmers - KDE compliant look-and-feel WARNING: Administrator have to see the README.Fedora file locate in the /usr/share/doc/pikdev-0.9.2 directory to complete full feature installation.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.9.2-6.fc9 0.9.2-6.fc9 0.9.2-7.fc11 0.9.2-7.fc11 0.9.2-8.fc12 0.9.2-8.fc12

    piklab

    Summary

    Piklab is a graphic development environment for PIC and dsPIC microcontrollers. It interfaces with various toochains for compiling and assembling and it supports several Microchip and direct programmers. WARNING: Administrator have to see the README.Fedora file locate in the /usr/share/doc/piklab-0.15.3 directory to complete full feature installation.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.15.3-2.fc10 0.15.3-2.fc10 0.15.3-3.fc11 0.15.3-3.fc11 0.15.3-4.fc12 0.15.3-4.fc12

    pikloops

    Summary

    PiKLoop generate for you code to create delays for Microchip PIC microcontrollers. It is an useful companion for Pikdev or Piklab IDE.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.2.5-3.fc9 0.2.5-3.fc9 0.2.5-4.fc11 0.2.5-4.fc11 0.2.5-5.fc12 0.2.5-5.fc12

    qtoctave

    Summary

    QtOctave is a frontend for Octave based on Qt4.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.8.1-0.20080823.svn165.fc10 0.8.1-0.20080823.svn165.fc10 0.8.1-0.20080825.svn165.fc11 0.8.1-0.20080825.svn165.fc11 0.8.1-0.20080826.svn165.fc12 0.8.1-0.20080826.svn165.fc12

    qucs

    Summary

    Qucs is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter and harmonic balance analysis.

    Supported Fedora branches

    4E 4E 5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel epel epel_testing updates updates_testing updates_testing updates updates updates_testing
    0.0.14-1.el4 0.0.14-1.el4 0.0.14-1.el5 0.0.14-1.el5 0.0.15-3.fc10 0.0.15-1.fc10 0.0.15-3.fc11 0.0.15-3.fc11 0.0.15-4.fc12 0.0.15-4.fc12

    rfdump

    Summary

    RFDump is a tool to detect RFID-Tags and show their meta information: Tag ID, Tag Type, manufacturer etc. The user data memory of a tag can be displayed and modified using either a Hex or an ASCII editor. Tag contents can be stored and loaded using a specific XML fomrat. This effectively allows to copy data from one tag to another. In addition, the integrated cookie feature demonstrates how easy it is for a company to abuse RFID technology to spy on their customers. RFDump works with the ACG Multi-Tag Reader or similar card reader hardware.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.6-3.fc10 1.6-3.fc10 1.6-4.fc11 1.6-4.fc11 1.6-5.fc12 1.6-5.fc12

    sdcc

    Summary

    SDCC is a C compiler for 8051 class and similar microcontrollers. The package includes the compiler, assemblers and linkers, a device simulator and a core library. The processors supported (to a varying degree) include the 8051, ds390, z80, hc08, and PIC.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    2.9.0-5.fc10 2.9.0-5.fc10 2.9.0-5.fc11 2.9.0-5.fc11 2.9.0-4.fc12 2.9.0-4.fc12

    sk2py

    Summary

    Sk2Py is an wxPython-based IDE which assists in the migration of Cadence Skill(tm)-based PCells to Python PyCells for use in all Open Access environments. Sk2Py is listed as a Fedora Electronic Lab (FEL) application.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    0.1-1.fc10 0.1-1.fc10 0.1-3.fc11 0.1-3.fc11 0.1-4.fc12 0.1-4.fc12

    tetex-IEEEtran

    Summary

    The IEEEtran class is the official LaTeX class for authors of the Institute of Electrical and Electronics Engineers (IEEE) transactions journals and conferences.

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    1.7.1-1.fc8 1.7.1-1.fc8 1.7.1-2.fc11 1.7.1-2.fc11 1.7.1-3.fc12 1.7.1-3.fc12

    tkcvs

    Summary

    TkCVS is a Tcl/Tk-based graphical interface to the CVS and Subversion configuration management systems. It will also help with RCS. TkDiff is included for browsing and merging your changes. TkCVS shows the status of the files in the current working directory, and has tools for tagging, merging, importing, exporting, checking in/out, and other user operations. TkCVS also aids in browsing the repository. For Subversion, the repository tree is browsed like an ordinary file tree. For CVS, the CVSROOT/modules file is read. TkCVS extends CVS with a method to produce a "user friendly" listing of modules. This requires special comments in the CVSROOT/modules file. Although TkCVS now supports Subversion, it will still work happily without it in your CVS directories. It didn't abandon CVS, it just grew some new capabilities.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    8.1-2.el5 8.1-2.el5 8.2-1.fc10 8.2-1.fc10
    Sun Dec 7 17:55:28 2008
    8.2-2.fc11 8.2-2.fc11 8.2-3.fc12 8.2-3.fc12

    tkgate

    Summary

    TkGate is a event driven digital circuit simulator based on Verilog. TkGate supports a wide range of primitive circuit elements as well as user-defined modules for hierarchical design.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    2.0-7.beta9.el5 2.0-7.beta9.el5 2.0-7.beta9.fc10 2.0-7.beta9.fc10 2.0-7.beta9.fc11 2.0-7.beta9.fc11 2.0-7.beta9.fc12 2.0-7.beta9.fc12

    toped

    Summary

    Toped is a layout editor with CIF and GDSII export capabilities. Toped is listed among Fedora Electronic Lab packages.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    0.9.2-2.el5 0.9.2-2.el5 0.9.5-1.fc10 0.9.5-1.fc10
    Sun Oct 4 13:56:51 2009
    0.9.5-1.fc11 0.9.5-1.fc11
    Sun Oct 4 13:59:27 2009
    0.9.5-1.fc12 0.9.5-1.fc12

    uisp

    Summary

    Uisp is utility for downloading/uploading programs to AVR devices. Can also be used for some Atmel 8051 type devices. In addition, uisp can erase the device, write lock bits, verify and set the active segment. For use with the following hardware to program the devices: pavr http://avr.jpk.co.nz/pavr/pavr.html stk500 Atmel STK500 dapa Direct AVR Parallel Access stk200 Parallel Starter Kit STK200, STK300 abb Altera ByteBlasterMV Parallel Port Download Cable avrisp Atmel AVR ISP (?) bsd http://www.bsdhome.com/avrprog/ (parallel) fbprg http://ln.com.ua/~real/avreal/adapters.html (parallel) dt006 http://www.dontronics.com/dt006.html (parallel) dasa serial (RESET=RTS SCK=DTR MOSI=TXD MISO=CTS) dasa2 serial (RESET=!TXD SCK=RTS MOSI=DTR MISO=CTS)

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    20050207-4.fc10 20050207-4.fc10 20050207-5.fc11 20050207-5.fc11 20050207-6.fc12 20050207-6.fc12

    verilator

    Summary

    Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Authors: -------- Wilson Snyder Paul Wasson Duane Galbi

    Supported Fedora branches

    f10 f10 f11 f11 f12 f12
    updates_testing updates updates_testing updates updates updates_testing
    3.712-1.fc10 3.712-1.fc10 3.712-1.fc11 3.712-1.fc11 3.712-1.fc12 3.712-1.fc12

    vhd2vl

    Summary

    vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthetisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    2.0-3.el5 2.0-3.el5 2.0-3.fc10 2.0-3.fc10 2.0-4.fc11 2.0-4.fc11 2.0-5.fc12 2.0-5.fc12

    vrq

    Summary

    VRQ is modular verilog parser that supports plugin tools to process verilog. Multiple tools may be invoked in a pipeline fashion within a single execution of vrq. It is a generic front-end parser with support for plugin backend customizable tools.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    1.0.63-1.el5 1.0.58-3.el5 1.0.63-1.fc10 1.0.63-1.fc10 1.0.63-1.fc11 1.0.63-1.fc11 1.0.62-1.fc12 1.0.62-1.fc12

    xcircuit

    Summary

    Xcircuit is a general-purpose drawing program and also a specific-purpose CAD program for circuit schematic drawing and schematic capture.

    Supported Fedora branches

    5E 5E f10 f10 f11 f11 f12 f12
    epel_testing epel updates_testing updates updates_testing updates updates updates_testing
    3.4.30-1.el5 3.4.30-1.el5 3.6.161-1.fc10 3.4.30-1.fc10 3.6.161-1.fc11 3.4.30-2.fc11 3.6.161-1.fc12 3.6.161-1.fc12

    Generated on Fri Nov 6 07:50:40 2009 by Chitlesh Goorah

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