--[an error occurred while processing this directive]
Fedora Electronic Lab
RTL and logic synthesis design flows
- Automatic schematic generation
- VHDL compilation and simulation
- Finite State Machines (FSM)
- Model checking and formal proof
- RTL and Logic synthesis
- Data-Path compilation
- Macro-cells generation
- Symbolic Pad cells
- Design rules checking
- Physical optimization and layout design flows.
- Complete RTL to CIF and GDSII flows.
- 7 extra standard cells up to a feature size of 0.13µm
- Read/write standard ins/outs including Verilog® and VHDL.
- Place and route
- Layout edition
- Automatic Layout generation
- Netlist extraction and verification
- Creates a POV-Ray (3D view) scene description file of the GDSII data.
[an error occurred while processing this directive]