Featured Solutions

The Fedora Electronic Laboratory includes design tools for:

ASIC Analog Circuit Design and Simulation
ASIC Layout, DRC and LVS
Digital Simulation and Verification
RTL and logic synthesis design flows
Circuit and PCB Layout
Micro Controller (µC) Programming and Embedded Systems Development
CAD Tools
Project Management and budget tracking

ASIC Analog Circuit Design and Simulation

This simulation lab enables design engineers to edit and simulate their schematics.

General Purpose Circuit Simulators (Analysis : Nonlinear AC/DC, Transient, Fourier, S-parameter and harmonic balance)
Beyond Spice capabilities: Level 49, BSIMv3 and EKV implementations
Multi-lingual, ability to mimic different variants of spice, and also supporting the newer languages like Verilog-AMS
Draws publishable-quality electrical circuit schematic diagrams.
Circuit components can be retrieved from libraries which are fully editable.

Tools:
gnucap - A general purpose circuit simulator with its engine designed to do true mixed-mode simulation. The developers thesis can be read here.
ngspice - A mixed level/signal circuit simulator
xcircuit - A general-purpose drawing program and also a specific-purpose CAD program for circuit schematic drawing and schematic capture.

ASIC Layout, DRC and LVS

A continuous DRC that operates in background and gives an up-to-date picture of violations.
A hierarchical circuit extractor that only re-extracts portions of the circuit that have changed.
Plowing that permits interactive stretching and compaction.
Routing tools that work under and around existing connections.
Logs and corner stitching to achieve efficient implementations.
Dedicated to training in sub-micron CMOS VLSI design with full editing facilities.
Supports technology files by the MOSIS foundry service.
Switch-level simulation of the layout, by considering transistors as ideal switches, or using RC time constants to predict the relative timing of events through extracted capacitance and lumped resistance values.
Ensures that layout connectivity matches the logical design represented by the schematic or netlist before tapeout by automatically extracting devices and nets formed across layout hierarchy and comparing them to the schematic netlist. (LVS) )
Generates GDS II stream format and CIF from a given layout.
Achievement : Thick-film circuit layout using the Magic layout editor.

Tools:
Magic - Widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.
Electric - A sophisticated electrical CAD system that can handle many forms of circuit design, including custom IC layout (ASICs), schematic drawing, hardware description language specifications, and electro-mechanical hybrid layout. View the IEEE Santa Clara Valley (June 4, 2009) presentation here.
Toped - A cross-platform VLSI IC layout editor.
Netgen - A tool for comparing netlists, in analog or mixed-signal circuits that cannot be simulated in reasonable time.

Digital Simulation and Verification

A HDL simulation environment that enables you to verify the functional and timing models of your design. Thus, your Design teams can focus on improving existing methodologies with tools that scale across multiple levels of abstraction and design complexity.

VPI functionality.
A graphical waveform viewer.
Supports both VHDL and Verilog designs.
A Verilog simulator and synthesis tool for IEEE 1364-2001 standard.
Export signals to a VCD file or a GHW file for visual inspection with a waveform viewer.
Pretty printing or cross references generation in HTML.
Makefile generation for any component in a design.
Achievements: Successfully compiled and run a DLX processor and a LEON1 SPARC processor.
Automatic layout generation from VHDL description via desired standard cell libraries.
Implementation of the VHDL language in accordance to the IEEE 1076-1987 standard, IEEE 1076-1993 standard, the protected types of VHDL00 (aka IEEE 1076a or IEEE 1076-2000) and and non-standard third party libraries.

Tools:
GHDL A VHDL simulator, using the GCC technology. GHDL implements the VHDL language according to the IEEE 1076-1987 or the IEEE 1076-1993 standard. It compiles VHDL files and creates a binary that simulates your design.
Qucs - A circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter and harmonic balance analysis.
FreeHDL - Yet another VHDL simulator.
Icarus Verilog A Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. More than a simulator.
GTKWave Waveform viewer that can view VCD files produced by most VHDL/Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools.
Drawtiming - A command line tool for generating timing diagrams from ASCII input files. The input files use a structured language to represent signal state transitions and interdependencies.

RTL and logic synthesis design flows

Automatic schematic generation
VHDL compilation and simulation
Finite State Machines (FSM)
Model checking and formal proof
RTL and Logic synthesis
Data-Path compilation
Macro-cells generation
Symbolic Pad cells
Design rules checking
Place and route
Layout edition
Netlist extraction and verification
Automatic Layout generation
Physical optimization and layout design flows
Complete RTL to CIF and GDSII flows
7 extra standard cells up to a feature size of 0.13µm
Read/write standard ins/outs including Verilog and VHDL
Creates a POV-Ray (3D view) scene description file of the GDSII data.

Tools:
pharosc VLSI and ASIC Technology Standard Cell Libraries
Alliance - a complete set of CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.
gds2pov - Creates attractive 3D pictures of a layout. Converts GDS2 layout file to POV-Ray

Circuit and PCB Layout

A professional-quality printed circuit board design environment along with :

schematic capture, simulation, prototyping attribute management,
bill of materials (BOM) generation and netlisting into over 20 netlist formats.
Includes a rats nest feature, design rule checking, and can provide industry standard RS-274-X (Gerber), NC drill, and centroid data (X-Y data) output for use in the board fabrication and assembly process.
Offers high end features such as an autorouter and trace optimizer, which can tremendously reduce layout time.
Creates PCB of up to 8 layers with an unlimited number of components and nets.
Includes a viewer for Gerber files (RS274X), which supports NC-drill and Excellon formats.

Tools:
PCB - An interactive printed circuit board editor.
Gerbv - Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files are generated from PCB CAD system and sent to PCB manufacturers as basis for the manufacturing process.
gEDA/gaf - A full suite of Electronic Design Automation tools.
Kicad - Kicad creates electronic schematic diagrams and printed circuit board artwork up to 16 layers.

CAD Tools

The CAD department of many semiconductor design centers maintain various scripts under various version control systems. We strives to give those CAD engineers some perl modules and a proper platform.

Revision Control : CVS, SVN, GIT, RCS
Web based tools : Trac, Bugzilla
UML to maintain their personalized perl scripts.

Perl Modules:

VHDL : perl-Hardware-Vhdl-Parser, perl-Hardware-Vhdl-Tidy, perl-Hardware-Vhdl-Lexer
Verilog : perl-Verilog perl-Verilog-CodeGen perl-Hardware-Verilog-Parser perl-Verilog-Readmem
Systemc : perl-SystemPerl perl-SystemC-Vregs (Read more about SystemC on Fedora here)
Generation of documentation : doxygen with VHDL support
SystemVerilog : perl-Verilog
Modelsim List: perl-ModelSim-List